Odysseus

The world of mobile devices is experiencing an ongoing trend of feature enhancement and device convergence. Ever-more sophisticated smartphones appear that incorporate technology that panders to our "gadget friendly mentality. For many, the mobile phone is now their phone, PDA, MP3/video player, email client and camera all in one! From a phone manufacturers perspective, intent on selling more of their devices, this is an ideal state of affairs—the device is now no longer "just" a phone but a general-purpose multimedia platform that can be leveraged by many different applications.

A key obstacle, however, in this spiral of feature enhancement and device convergence is that the consumer does not expect any decrease in satisfaction in the mobile experience, such as shortened battery life, whilst at the same time expecting slim hand-held devices. This presents significant challenges to those who design hardware for multimedia platforms. All of the applications referred to above require dealing with large amounts of audio/video data—arguably the most computationally demanding form of data to process and increased computation means increased power consumption, which means shorter battery life. For this reason, power efficiency in general is a key concern for those manufacturing future generations of devices. Given the range of applications being dreamt up, another key concern is hardware flexibility—the ability to be able to adapt the same multimedia platform to many different applications thereby efficiently re-using the same basic architecture.

The Hardware Group in the Centre for Digital Video Processing (CDVP) has just started a 3- year Enterprise Ireland Technology Development project, entitled PAMPAS (Power-aware Multimedia Platforms and Applications) that sets out the group's research agenda for the foreseeable future and that addresses key challenges in this area. The goal of the project is to research and develop flexible and configurable hardware accelerator cores for a range of power-aware basic enabling video processing technologies. These architectures will be wrapped in a specifically designed hardware (HW) application programming interface (API) that will handle the run time re-configuration of the hardware accelerator for a given video processing functionality for a given target device and a software (SW) API that will facilitate the integration of the HW block (together with its HW API) within target applications. In order to validate these hardware cores, they are integrated into application demonstrators e.g. low-power real-time face detection on a mobile (ARM-based) platform. The purpose of this internship is to work alongside the researchers currently developing these demonstrators. Given the steep learning curve associated with the hardware design and synthesis process, initially the internship will most likely focus on developing pure software implementations of demonstrators to act as benchmarks for the low-power hardware/software solutions and as a basis for further development in subsequent years.

Relevance of Project to the Host Laboratories:

A team of 1 postdoc, 2 PhDs and 1 research assistant are currently working in this area, with more recruitment expected in early 2006. Whilst the team are working on both developing HW cores and the associated SW/HW API that adds adaptability, the real value of these outputs will lie in their demonstration. Thus, project demonstrators of different AV functionality on a range of mobile platforms is a key ancillary objective. The proposed project directly contributes to this.

Supervisors:

Dr. Noel E. O'Connor (AIC, DCU)

Keywords:

Low-power hardware; audiovisual processing cores.